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a
120 mA Switched Capacitor Voltage Inverter with Regulated Output ADP3605
FUNCTIONAL BLOCK DIAGRAM
CP+ S PD S1 CP- DN S S3 B SND S2 DNS S4 VOUT VIN
FEATURES Fully Regulated Output Voltage (-3 V and Adjustable) High Output Current: 120 mA Output Accuracy: 3% 250 kHz Switching Frequency Low Shutdown Current: 2 A Typical Input Voltage Range from 3 V to 6 V SO-8 and RU-14 Packages -40 C to +85 C Ambient Temperature Range APPLICATIONS Voltage Inverters Voltage Regulators Computer Peripherals and Add-On Cards Portable Instruments Battery Powered Devices Pagers and Radio Control Receivers Disk Drives Mobile Phones
ADP3605
SD
OSC CLOCK GEN
FEEDBACK CONTROL LOOP
VSENSE
GND
GENERAL DESCRIPTION
The ADP3605 is a 120 mA regulated output switched capacitor voltage inverter. It provides a regulated output voltage with minimum voltage loss and requires a minimum number of external components. In addition, the ADP3605 does not require the use of an inductor. Pin-for-pin and functionally compatible with the ADP3604, the internal oscillator of the ADP3605 runs at 500 kHz nominal frequency which produces an output switching frequency of 250 kHz. This allows for the use of smaller charge pump and filter capacitors. The ADP3605 provides an accuracy of 3% with a typical shutdown current of 2 A. It can also operate from a single positive input voltage as low as 3 V. The ADP3605 is offered with the regulation fixed at -3 V or adjustable via external resistors over a -3 V to -6 V range.
VIN *CIN 4.7 F
+ *CP 4.7 F +
VIN CP+
VOUT +
-3.0V *CO 4.7 F
ADP3605-3
CP-
OFF
SD ON 0
GND
VSENSE
*FOR BEST PERFORMANCE, 10 F IS RECOMMENDED CP : SPRAGUE, 293D475X0010B2W CIN, CO: TOKIN, 1E475ZY5UC205F
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADP3605-SPECIFICATIONS1, 2, 3 (V
Parameter OPERATING SUPPLY RANGE SUPPLY CURRENT Shutdown Mode OUTPUT VOLTAGE4 Symbol VS IS
IN
= 5.0 V @ TA = +25 C, CP = CO = 4.7 F unless otherwise noted)
Min 3 Typ 5 3 2 -3.09 -3.15 -3.0 -3 Max 6 6 15 -2.91 -2.85 Units V mA A V V
Conditions
-40C < TA < +85C VSD = VIN -40C < TA < +85C IO = 60 mA IO = 10 mA-120 mA, -40C TA +85C 4.75 V VS 6.0 V IO = 10 mA-60 mA IO = 10 mA-120 mA
VO
LOAD REGULATION OUTPUT RESISTANCE Open Loop OUTPUT RIPPLE VOLTAGE
VO/IO
0.3 0.25 9
mV/mA mV/mA mV mV 288 kHz
RO VRIPPLE CIN = CO = 4.7 F, ILOAD = 60 mA ILOAD = 120 mA VIN = 5 V -40C < TA < +85C 212
38 75 250
SWITCHING FREQUENCY SHUTDOWN Logic Input High Input Current Logic Input Low Input Current
FS
VIH IIH VIL IIL
2.4 1 0.4 1
V A V A
NOTES 1 Capacitors CIN, CO and CP in the test circuit are 4.7 F with 0.1 ESR. 2 See Figure 1 Conditions. 3 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 4 For the adjustable device, a 1% resistor should be used to maintain output voltage tolerance. For both device types, tolerances can be improved by >1% using larger value and lower ESR capacitors for C O and C P. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
Input Voltage (V+ to GND, GND to OUT) . . . . . . . . +7.5 V Input Voltage (V+ to OUT) . . . . . . . . . . . . . . . . . . . . . +11 V Output Short Circuit Protection . . . . . . . . . . . . . . . . . . . 1 sec Power Dissipation, SO-8 . . . . . . . . . . . . . . . . . . . . . . 660 mW JA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C/W Power Dissipation, RU-14 . . . . . . . . . . . . . . . . . . . . . 600 mW JA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165C/W Operating Temperature Range . . . . . . . . . . . -40C to +85C
Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. 2 JA is specified for worst case conditions with device soldered on a circuit board.
ORDERING GUIDE
Model ADP3605AR-3 ADP3605AR ADP3605ARU-3
Output Voltage -3 V ADJ -3 V
Package Description Small Outline Small Outline Thin Shrink Small Outline Package (TSSOP)
Package Options* SO-8 SO-8 RU-14
*Contact the factory for the availability of other output voltage options.
-2-
REV. A
ADP3605
Table I. Other Members of ADP36xx Family 1 PIN FUNCTION DESCRIPTIONS
Model
Output Package Current Option2
Comments
ADP3603AR 50 mA ADP3604AR 120 mA ADP3610ARU 320 mA
SO-8 Nom.-3 3% Inverter SO-8 Nom.-3 3% Inverter TSSOP-16 Nom. 3.3 VIN Doubler
Pin Pin SO-8 TSSOP Name 1 2 3 4 4 5 6 7 CP+ GND CP- SD
Function Positive Terminal for the Pump Capacitor. Device Ground. Negative Terminal for the Pump Capacitor. Logic Level Shutdown Pin. Apply a logic high or connect to VIN to shutdown the device. In shutdown mode, the charge pump is turned off and quiescent current is reduced to 2 A (typical). Apply a logic low or connect to ground for normal operation. Output Voltage Sense Line. This is used to improve load regulation by eliminating IR drop on the high current carrying output traces. For normal operation, connect VSENSE to VOUT. See Application section for more detail.
NOTES 1 See individual data sheets for detailed ordering information. 2 SO = Small Outline; TSSOP = Thin Shrink Small Outline Package.
Table II. Alternative Capacitor Technologies
Type Aluminum Electrolytic Capacitor Multilayer Ceramic Capacitor Solid Tantalum Capacitor OS-CON Capacitor
Life
High Freq
Temp
Size
Cost
Fair
Fair
Fair
Small
Low
5
8
VSENSE
Long Above Avg Above Avg
Good
Poor
Fair1
High
Avg Good
Avg Good
Avg Good
Avg Avg
6
NOTE 1 Refer to capacitor manufacturer's data sheet for operation below 0C.
7
1, 2, 3, 9, 12, 13, 14 10
NC VOUT
Table III. Recommended Capacitor Manufacturers
Manufacturer Sprague Sprague Nichicon Mallory TOKIN MuRata
Capacitor 672D, 673D, 674D, 678D 675D, 173D, 199D PF and PL TDC and TDL MLCC GRM
Capacitor Type Aluminum Electrolytic Tantalum Aluminum Electrolytic Tantalum Multilayer Ceramic Multilayer Ceramic
8
11
VIN
No Connection. Regulated Negative Output Voltage. Connect a low ESR, 4.7 F or larger capacitor between this pin and device GND. Positive Supply Input Voltage. Connect a low ESR bypass capacitor between this pin and device ground to minimize supply transients.
PIN CONFIGURATIONS RU-14
NC NC NC CP+ GND CP- SD NC NC NC VIN VOUT NC VSENSE
CP+ 1 GND 2
SO-8
8
VIN VOUT
ADP3605
ADP3605
7
TOP VIEW CP- 3 (Not to Scale) 6 NC SD 4
5
VSENSE
NC = NO CONNECT
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3605 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges larger than 600 V HBM. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADP3605 -Typical Performance Characteristics
270 OSCILLATOR FREQUENCY - kHz 4.5 VIN = +5V 4 2.5 -2.97 OUTPUT VOLTAGE - Volts IL = 120mA 3 -2.96
SUPPLY CURRENT - mA IN NORMAL MODE
SUPPLY CURRENT - A IN SHUTDOWN MODE
3.5
SHUTDOWN MODE (VSD = VIN)
2
-2.98 -2.99 IL = 60mA -3.00 -3.01 -3.02 -3.03 -40 IL = 10mA
260
3 NORMAL MODE (VSD = 0V) 2.5 2 1.5 -40
1.5
1
0.5 0 85
250
3
3.5 4 4.5 5 5.5 SUPPLY VOLTAGE - Volts
6
-15
10 35 60 TEMPERATURE - C
-15
10 35 60 TEMPERATURE - C
85
Figure 2. Oscillator Frequency vs. Supply Voltage
Figure 3. Supply Current vs. Temperature
Figure 4. Output Voltage vs. Temperature
300 OSCILLATOR FREQUENCY - kHz
140 120
-2.5 VIN = +3V -2.6
OUTPUT VOLTAGE - Volts
280
VIN = +3.5V VIN = +4.75V
INPUT CURRENT - mA
100 80 60 40 20
-2.7 -2.8 VIN = +5V -2.9 -3.0 -3.1 -3.2 VIN = +6V
260
240
220
200 -40
-15
10 35 60 TEMPERATURE - C
85
0 10
30
50 70 90 110 LOAD CURRENT - mA
130
0
40
80 120 160 200 LOAD CURRENT - mA
240
280
Figure 5. Oscillator Frequency vs. Temperature
Figure 6. Average Input Current vs. Output Current
Figure 7. Output Voltage vs. Load Current
3.5 3 NORMAL MODE (VSD = 0V)
7 6 5 4 3 SHUTDOWN MODE (VSD = VIN) 2 1 0
SUPPLY CURRENT - mA IN NORMAL MODE
2.5 2 1.5 1 0.5 0
3
5 4 SUPPLY VOLTAGE - Volts
6
SUPPLY CURRENT - A IN SHUTDOWN MODE
Figure 8. Supply Current vs. Supply Voltage
Figure 9 . Start-Up Under Full Load
Figure 10. Enable/Disable Time Under Full Load
-4-
REV. A
ADP3605
THEORY OF OPERATION
The ADP3605 uses a switched capacitor principle to generate a negative voltage from a positive input voltage. An onboard oscillator generates a two phase clock to control a switching network that transfers charge between the storage capacitors. The switches turn on and off at a 250 kHz rate, which is generated from an internal 500 kHz oscillator. The basic principle behind the voltage inversion scheme is illustrated in Figures 11 and 12.
VIN S1 CP S2 + - S4 CO VOUT S3
Temperature is another factor affecting capacitor performance. Figure 13 illustrates the temperature effect on various capacitors. If the circuit has to operate at temperatures significantly different from 25C, the capacitance and ESR values must be carefully selected to adequately compensate for the change. Various capacitor technologies offer improved performance over temperature; for example, certain tantalum capacitors provide good low-temperature ESR but at a higher cost. Table II provides the ratings for different types of capacitor technologies to help the designer select the right capacitors for the application. The exact values of CIN and CO are not critical. However, low ESR capacitors such as solid tantalum and multilayer ceramic capacitors are recommended to minimize voltage loss at high currents. Table III shows a partial list of the recommended low ESR capacitor manufacturers.
Input Capacitor
Figure 11. ADP3605 Switch Configuration Charging the Pump Capacitor
During phase one, S1 and S2 are ON, charging the pump capacitor to the input voltage. Before the next phase begins, S1 and S2 are turned OFF as well as S3 and S4 to prevent any overlap. S3 and S4 are turned ON during the second phase (see Figure 12) and charge stored in the pump capacitor is transferred to the output capacitor.
VIN S1 CP S2 + - S4 CO VOUT S3
A small 1 F input bypass capacitor, preferably with low ESR, such as tantalum or multilayer ceramic, is recommended to reduce noise and supply transients and supply part of the peak input current drawn by the ADP3605. A large capacitor is recommended if the input supply is connected to the ADP3605 through long leads, or if the pulse current drawn by the device might affect other circuitry through supply coupling.
Output Capacitor
Figure 12. ADP3605 Switch Configuration Charging the Output Capacitor
During the second phase, the positive terminal of the pump capacitor is connected to ground through variable resistance switch, S3, and the negative terminal is connected to the output, resulting in a voltage inversion at the output terminal. The ADP3605 block diagram is shown on the front page.
APPLICATION INFORMATION Capacitor Selection
The output capacitor (CO) is alternately charged to the CP voltage when CP is switched in parallel with CO. The ESR of CO introduces steps in the VOUT waveform whenever the charge pump charges CO, which contributes to VOUT ripple. Thus, ceramic or tantalum capacitors are recommended for CO to minimize ripple on the output. Figure 14 illustrates the output ripple voltage effect for various capacitance and ESR values. Note that as the capacitor value increases beyond the point where the dominant contribution to the output ripple is due to the ESR, no significant reduction in VOUT ripple is achieved by added capacitance. Since output current is supplied solely by the output capacitor, CO, during one-half of the charge-pump cycle, peak-to-peak output ripple voltage is calculated by using the following formula.
VRIPPLE =
IL 2 x FS x CO
+ 2 x I L x ESRCO
The ADP3605's high internal oscillator frequency permits the use of small capacitors for both the pump and the output capacitors. For a given load current, factors affecting the output voltage performance are: * Pump (CP) and output (CO) capacitance. * ESR of the CP and CO. When selecting the capacitors, keep in mind that not all manufacturers guarantee capacitor ESR in the range required by the circuit. In general, the capacitor's ESR is inversely proportional to its physical size, so larger capacitance values and higher voltage ratings tend to reduce ESR. Since the ESR is also a function of the operating frequency, when selecting a capacitor, make sure its value is rated at the circuit's operating frequency.
where: IL = Load Current FS = 250 kHz nominal switching frequency CO = 10 F with an ESR of 0.15
VRIPPLE = 120 mA 2 x 250 kHz x 10 F + 2 x 120 mA x 0.15 = 60 mV
Multiple smaller capacitors can be connected in parallel to yield lower ESR and lower cost. For lighter loads, proportionally smaller capacitors are required. To reduce high frequency noise, bypass the output with a 0.1 F ceramic capacitor in parallel with the output capacitor.
REV. A
-5-
ADP3605
Pump Capacitor Improved Load Regulation
The ADP3605 alternately charges CP to the input voltage when CP is switched in parallel with the input supply, and then transfers charge to CO when CP is switched in parallel with CO. During the time CP is charging, the peak current is approximately two times the output current. During the time CP is delivering charge to CO, the supply current drops down to about 3 mA. A low ESR capacitor has much greater impact on performance for CP than CO since current through CP is twice the CO current. Therefore, the voltage drop due to CP is about four times the ESR of CP times the load current. While the ESR of CO affects the output ripple voltage, the voltage drop generated by the ESR of CP, combined with the voltage drop due to the output source resistance, determines the maximum available VOUT.
10 ALUMINUM
In most applications, the IR drop from printed circuit board traces is not critical. VSENSE should be connected to the output at a convenient PCB location close to the load. However, if a reduction in IR drop or improvement in load regulation is desired, the sense line can be used to monitor the output voltage at the load. To avoid excessive noise pickup, keep the VSENSE line as short as possible and away from any noisy line.
Shutdown Mode
The ADP3605's output can be disabled by pulling the SD pin (Pin 4) high to a TTL/CMOS logic compatible level which will stop the internal oscillator. In shutdown mode, the quiescent current is reduced to 2 A (typical). Applying a digital low level or tying the SD Pin to ground will turn on the output. If the shutdown feature is not used, Pin 4 should be tied to the ground pin.
Power Dissipation
The power dissipation of the ADP3605 circuit must be limited such that the junction temperature of the device does not exceed the maximum junction temperature rating. Total power dissipation is calculated as follows: P = (VIN -|VOUT|) IOUT + (VIN) IS
1.0
ESR -
CERAMIC
TANTALUM 0.1 ORGANIC SEMIC
Where IOUT and IS are output current and supply current, VIN and VOUT are input and output voltages respectively. For example: assuming worst case conditions, VIN = 6 V, VOUT = -2.9 V, IOUT = 120 mA and IS = 5 mA. Calculated device power dissipation is:
0 50 TEMPERATURE - C 100
0.01 -50
P (6 V-|-2.9 V|)(0.12) + (6 V)(0.005 A) = 402 mW This is far below the 660 mW power dissipation capability of the ADP3605 in SO-8 or 600 mW in RU-14
General Board Layout Guidelines
Figure 13. ESR vs. Temperature
100 ADP3605-3 80
OUTPUT RIPPLE - mV
Since the ADP3605's internal switches turn on and off very fast, good PC board layout practices are critical to ensure optimal operation of the device. Improper layouts will result in poor load regulation, especially under heavy loads. Following these simple layout guidelines will improve output performance. 1. Use adequate ground and power traces or planes. 2. Use single point ground for device ground and input and output capacitor grounds. 3. Keep external components as close to the device as possible. 4. Use short traces from the input and output capacitors to the input and output pins respectively.
60
150m 40 100m 20 50m 0
0
20
40
60 80 100 CAPACITANCE - F
120
140
160
Figure 14. Output Ripple Voltage (mV) vs. Capacitance and ESR
-6-
REV. A
ADP3605
Maximum Output Voltage
Maximum unregulated output voltage can be obtained on the ADP3605-3 by connecting the VSENSE pin to ground instead of to the VOUT pin. Under this condition, the magnitude of the unregulated output voltage depends on the load current. VOUT is inversely proportional to the load current as illustrated in Figure 15.
-5.0
High accuracy on the adjustable output voltage is achieved with the use of precision trimmed internal resistors, which eliminates the need to trim the external resistor or add a second resistor to form a divider. The adjustable output voltage is set using the following formula:
V OUT = -
1.5 R 9.5 k
where VOUT is in volts and R is in k.
Regulated Dual Supply System
VOUT - Volts
The circuit in Figure 18 provides regulated positive and negative voltages for systems that require dual supplies from a single battery or power supply.
-4.0
VIN = +5.0V
ADP3605-3
ADP3605
VIN = +5V CIN 4.7 F + CP + 4.7 F VIN CP+ CP- SD GND D1 1N5817 VOUT R1 44.2k CO + 4.7 F
VSENSE
-3.0 0 20 40 60 80 LOAD CURRENT - mA 100 120
Figure 15. Maximum Unregulated Output Voltage
Regulated Adjustable Output Voltage
+ C1 4.7 F
D2 1N5817
+
10 F
For the adjustable version of the ADP3605, the regulated output voltage is programmed by a resistor which is inserted between the VSENSE and VOUT pins, as illustrated in Figure 16. The inherent limit of the output voltage of a single inverting charge pump stage is -1 times the input voltage. The inverse (i.e., negative) scaling factor of 1.00 is reduced somewhat due to losses that increase with output current. To increase the scaling factor to attain a more negative output voltage, an external pump stage can be added with just passive components as shown in Figure 17. That single stage increases the inverse scaling factor to a limit of two, although the diode drops will limit the ability to attain that exact 2.00 scaling factor noticeably. Even further increases can be achieved with more external pump stages.
-5.0
Figure 17. Regulated -7 V from a 5 V Input
1N5817
ADP3607-5
VIN = +3.3V 10 F + CP1 10 F + VIN CP+ CP- SD GND VOUT +C +5V
O1
10 F VSENSE
ADP3605
VIN CP2 10 F CP+ CP- SD GND VOUT -2.6V R1 16.5k 1% CO2 +10 F
+
VSENSE
R = 29k
VOUT - Volts
Figure 18. Dual Supply System
-4.0 R = 24k
VIN = +5.0V VOUT
ADP3605
R
-3.0 0 20 40 60 80 LOAD CURRENT - mA 100 120
Figure 16. Adjustable Regulated Output Voltage
REV. A
-7-
ADP3605
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Small Outline IC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
14-Lead Thin Shrink Small Outline Package (TSSOP) (RU-14)
0.201 (5.10) 0.193 (4.90)
14 8
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.177 (4.50) 0.169 (4.30)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.256 (6.50) 0.246 (6.25)
1 7
0.0196 (0.50) x 45 0.0099 (0.25)
0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8 0 0.0500 (1.27) 0.0160 (0.41)
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
SEATING PLANE
8 0
0.028 (0.70) 0.020 (0.50)
-8-
REV. A
PRINTED IN U.S.A.
C3325a-0-7/99

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